library ieee;
use ieee.std_logic_1164.all;

entity decode is
    port(
    RegWrite, clk:
        in std_logic;
    A3:
        in std_logic_vector(4 downto 0);
    InstrD, Wd3, PCPlus4InD:
        in std_logic_vector(31 downto 0);

    RtD, RdD:
        out std_logic_vector(4 downto 0);
    SigImmD, RD1D, RD2D, PCPlus4OutD:
        out std_logic_vector(31 downto 0);
    MemToRegD, MemWriteD, BranchD, AluSrcD, RegDstD, RegWriteD, JumpD:
        out std_logic;
    AluControlD:
        out std_logic_vector(2 downto 0)
    );
end decode;

architecture behav of decode is
    component controller
        port(
        Op, Funct: in std_logic_vector(5 downto 0);
        MemToReg, MemWrite, Branch, AluSrc, RegDst, RegWrite, Jump:
        out std_logic;
        AluControl: out std_logic_vector(2 downto 0)
        );
    end component;

    component signext
        port(
        a: in std_logic_vector(15 downto 0);
        y: out std_logic_vector(31 downto 0)
        );
    end component;

    component regfile is
        port(
        ra1, ra2, wa3: in std_logic_vector(4 downto 0);
        wd3: in std_logic_vector(31 downto 0);
        clk, we: in std_logic;
        rd1, rd2: out std_logic_vector(31 downto 0)
        );
    end component;

begin
    ID_controller: controller
        port map(InstrD(31 downto 26), InstrD(5 downto 0),
                 MemToRegD, MemWriteD, BranchD, AluSrcD, RegDstD, RegWriteD,
                 JumpD, AluControlD);

    ID_regfile: regfile
        port map(InstrD(25 downto 21), InstrD(20 downto 16),
                 A3, Wd3, clk, RegWrite, RD1D, RD2D);

    ID_signext: signext
        port map(InstrD(15 downto 0), SigImmD);

    RtD <= InstrD(20 downto 16);
    RdD <= InstrD(15 downto 11);
    PCPlus4OutD <= PCPlus4InD;
end behav;
